This invention relates to the field of semiconductor processes that are compatible with scaling down of devices to smaller sizes and increasing the complexity of the metal and polysilicon interconnect patterns coupling various devices on the die to each other. More particularly, the invention relates to a process for creating a planarized layer of germanosilicate glass between polysilicon and some types of metal interconnect layers.
One of the major problems in semiconductor device fabrication is to make devices ever more complex without increasing the size of the die. Increased die size decreases yield and increases cost. However, to increase complexity on an integrated circuit die requires that thousands of transistors be interconnected into very complex circuit patterns. The interconnection patterns that result are very complicated and involve many crossing conductors. However in integrated circuit fabrication conductors are usually formed in polysilicon or metals like aluminum, titanium or tungsten by photolithography processes. This involves projecting light patterns on a two dimensional plane to form a two dimensional pattern in the conductor after performing certain etching steps that are well known. This is fine as long as one desires that at every place that two conductors cross each other that there be a circuit connection. However, where two conductors which cross each other are not supposed to be in electrical contact with each other, there is a problem in making a crossover or crossunder such that the two conductors do not make electrical contact with each other. These problems grow in number as device complexity increases. One way of alleviating this problem is to add a second layer of conductor over the first conductor layer and separating the two by an insulating layer. This process of adding conductive layers can be repeated as many times as necessary.
However these intermediate layers of insulating material must be flat and of high integrity to be effective. The insulating layer must be of high integrity. i.e., no pinholes or cracks, so as to prevent shorts between layers or open circuits in the layers above it caused by failure of the layers deposited above to fill in the cracks in the insulator. The insulator must be flat to have good photolithography characteristics. Major problems are created in forming subsequent layers using photolithography when trying to project very fine and closely spaced patterns of light onto a non-flat surface. Such problems include depth of field difficulties and other well known problems.
Further, the insulating layer which is used should be relatively free of dopants such as phosphorus which could come out of the insulating layer and enter portions of the structure surrounding the insulating layer during later high temperature processing steps.
Further, these intermediate insulating layers must have a coefficient of thermal expansion which substantially matches that of the underlying layers. This prevents cracking of the insulating layer caused by uneven thermal expansions in different layers in the structure during later high temperature processing steps or thermal cycling during service of the device in the field.
Many integrated devices today use doped polysilicon for a first conductive layer. In the prior art phosphorous doped silicon dioxide or plain silicon dioxide or germanosilicate glasses have been deposited over this polysilicon by chemical vapor deposition or low pressure chemical vapor deposition. This is an expensive and time consuming process, not usually done in a more efficient cassette to cassette operation. Further many of the gases used in the chemical vapor deposition processes can be toxic, flammable or corrosive or all three.
Further, many chemical vapor deposition processes exhibit enhanced deposition at sharp corners under most reaction conditions. For example, FIG. 1 shows an etched polysilicon step 10 on a substrate 12. A film 14 of silicon dioxide has been deposited by chemical vapor deposition. The line 15 shown in phantom represents the surface of a layer of spun-on glass, and illustrates the differences in planarizaticn which result from the two different processes of depositing insulating material. For chemical vapor deposition processes, the sharp points 16 and 18 of the polysilicon step 10 cause increased chemical activity in these regions, which results in the bulges 20 and 22 being formed in the film 14 near the cornets 16 and 18. Immediately below these bulges, microcracks 24 and 26 can form. These cracks are extremely difficult to cover completely with metal, and can lead to open circuits. This bulge formation process is intrinsic to the chemical vapor deposition process under most conditions. Further, this creates a non-flat surface upon which to do subsequent photolithography. Non-flat surfaces make the projection of light to define images in photoresist of closely spaced conductors or other features on subsequent layers difficult or impossible. Further, non-flat surfaces such as that presented by the top surface of the oxide layer 14 with microcracks make it extremely difficult to deposit uniform films of metal with high integrity i.e., no cracks or crevices in the metal film which can lead to open circuits in conductors which are supposed to be continuous.
In contrast, notice the relatively smooth geometry of the top surface 14 of the spun-on glass. This gently rolling surface makes it simple to deposit high integrity metal films from which interconnection wires can be formed with no fear of open circuits. Likewise, if another layer of spun-on glass is added, the resulting surface is flat or almost flat, and photolithography to form very fine features which are closely spaced becomes possible.
Chemical vapor deposition processes are also high temperature processes generally with typical reaction temperatures for formation of silicon dioxide films ranging from 400 to 900 degrees centigrade depending upon the gases and chemical reactions used to form the film. These higher temperatures preclude use of these processes over some structures which are temperature sensitive. Further, these high deposition temperatures can cause lateral and other undesired diffusion of dopants previously in other locations on the integrated circuit. This can cause undesirable effects such as changes in base width or channel length in transistors previously formed.
Finally uniformity of film coverage and flatness in regions away from corners of steps and trenches is generally not consistent in chemical vapor deposition processes.
It is known that the CVD process can be avoided by using a spin method to spin on coatings of silicon dioxide. In these methods, a modified alcoholic solution of tetraethoxygermane (hereafter TEOS) can be spun onto a silicon wafer, heated appropriately and a glassy silicon dioxide film will be formed. This eliminates some of the disadvantages of CVD and LPCVD processes, but leaves a major disadvantage. The major problem with this technique is that above a thickness range of approximately 3000 angstroms, the film develops cracks. These cracks are totally unacceptable since they decrease yield and render the devices unreliable.
Stress in films deposited on wafers is a function of the degree of mismatch in the coefficient of thermal expansion and the thickness of the film. Higher degrees of mismatch cause more stress as do thicker films. Various modifiers can be added to the solution, but useful thicknesses of 7,000-10,000 angstroms have not been achieved to data.
Therefore a need has arisen for a method of depositing a dopant free insulator film that was flat, had high integrity, was cheap and fast, and which could be deposited at a lower temperature and which resulted in a film which had a good match in thermal coefficient with the underlying structure.